FPFA silicon based electrode-layer design and fabrication

Multi Electrode Arrays (MEAs)


ELayer

Electronic layer and a section view respecting microelectrode arrays of the FPFA-chip (dimensions 28 x 32 mm).

Fabrication flow


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Our detection platform based on a hybrid chip containing a silicon substrate with integrated gold electrodes and a plastic fluidic layer, which consists of a network of channels and microreactor compartments. The microelectrode arrangements act as actuator components in our proposed reconfigurable microreactor networks and are design-optimized by computer simulation technics. The dimensions of a single FPFA-chip are 28 x 32 mm and supports lithographically structured gold wires leading individually from a multitude of microelectrode-arrays to ball-grid connector pads for a FPGA (Field Programmable Gate Array) and to an external connector.

The fabrication process for the electrode layer of the FPFA-chip which we have enhanced in cooperation with the technical team of the Center of Advanced European Studies and Research (caesar).

A 6" wafer provides the electrical layer for 16 FPFAs. The process flow starts with lithographic steps for embedding and structuring the metal layer containing the electrodes, wires and contact pads. The following step is a plasma-enhanced chemical vapour deposition (CVD) of the SiO2 passivation layer. After opening the passivation layer at the electrodes and conducting pad areas, fluidic I/O holes were placed using deep etching by an inductively coupled plasma  (ICP) to allow a reverse side fluidic connector to be used.
The resulting silicon chip (right image) supports lithographically structured gold wires leading individually from a multitude of microelectrode-arrays to ball-grid connector pads for a FPGA and to an external connector. The microelectrodes have dimensions from 10 to 40 μm in width and up to 200 μm in length with spacings between 10 and 200 μm.

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